I. Field of the Disclosure
The technology of the disclosure relates generally to handling of power-on conditions for memory devices, including for memory pre-decoding devices.
II. Background
In high speed memories, multiple pulsed latches are used to store decoded address values. These pulsed latches may be employed in memory decoding devices for a memory, such as memory pre-decoders and memory decoders. In the example of memory pre-decoders, the pulsed latches are configured to receive and store a portion of a memory address to be pre-decoded. The memory pre-decoder is configured to activate one of a plurality of pre-decoded address outputs provided to a memory decoder to select the memory word line corresponding to the memory address.
Following power-on of a device employing pulsed latch memory, the state of the pulsed latches is an unknown condition. Thus, to avoid unintentional selection of a random word line in the memory according to unknown states of the pulsed latches, the memory system is designed to prevent access before the pulsed latches are reset to a known default condition. As one example, an external reset signal generated after a power-on condition, (e.g., a system reset signal), may be provided to reset the pulsed latches. However, the external reset signal may be controlled by central processing unit (CPU) software or other system circuitry outside the memory system that is not quickly available after power-on. Therefore, valid memory accesses may not available during this time, thus increasing the time for power-on readiness of a device. If memory accesses were made available before an external reset signal becomes available, the unknown state of the pulsed latches could cause a random memory word line to be selected based on the random, unknown state of the pulsed latches. As an example, this could cause a run-time error to occur if a CPU attempts to execute an instruction at a word line in memory selected by pulsed latches in an unknown state.